1 Why is it important to keep clocks synchronized, i.e., what is the significance of clock synchronization?

A: The role of clock synchronization is to maintain the synchronization of data transmission between various network elements on the same MESH network, i.e., to ensure that the clock rate of transmission and the rate of reception are within a reasonable margin of error, so as to ensure the correct transmission and processing of data.

2 What kinds of clock signals are provided by the clock module and what are the functions of each clock signal?

A: The clock module mainly provides 38M system clock and 2K frame header control signals.

38M system clock: It is provided to the cross module, line module and branch module as the reference clock, so that the clock frequency of the line, branch and internal bus of the cross system is the same, which is convenient for service cross-connection.

The 2K frame header control signal is mainly used to control the position of the service frame header sent to the system side by the line and branch modules, so as to ensure that the position of the service bus frame header (the position of the F628) sent to the side of the crossover module by each slot is consistent. This ensures that the position of the frame header (F628 position) is the same for each slot to the system side of the cross module.

3 What are the clock operating modes and how are they switched?

A: There are three main clock operating modes, namely tracking mode, hold mode and free oscillation mode.

In the default case, the system clock is the internal source, in a free oscillation mode, when the artificial configuration of the available clock sources, the clock module into the tracking mode, when the configuration of the system priority table all reference sources are lost or there are alarms, the system clock tracking to the internal source, the clock module to enter the holding mode, that is, the DSP records the history of phase-locked data from the RAM to recover for the empirical phase-locked, the clock level is reduced to a device-level clock, with the longer the hold time, the worse the clock accuracy, until all the hold data is used up, the clock module enters the free oscillation mode of operation, the DSP directly controls half of the crystal voltage control voltage and maintains the value unchanged.

4 What are the types of clock protection? How does it invert the clock source in various modes?

A: There are three main types of clock protection modes, namely, clock priority mode, standard SSM mode, and extended SSM mode;

Clock Priority Mode: It is also the usual default clock protection mode, which is mainly based on the configured clock priority table for clock source protection, and when and only when the high priority clock source is lost, it will be switched to other clock sources for clock protection.

Standard SSM mode: must be started in the SSM protocol, there is a cross-clocking module to extract the clock priority table clock source ground S1 byte, according to the S1 byte for clock source protection. And in the case of two clock sources of the same quality level, and then according to the clock priority mode for source selection.

Extended SSM mode: that is, on the basis of the standard SSM mode, the ITU-T undefined S1 byte of the high 4bit to use to pass the clock ID, which can effectively prevent the occurrence of clock into a ring phenomenon in some specific environments, the mode of protection is still consistent with the standard SSM mode.

5 Delay time and wait for the recovery time of the two differences and use?

A: The delay time refers to the current tracking source failure, the delay in the clock source to switch the waiting time, the general delay time requirements in the 300-1800ms, that is to say, the current tracking source failure, not immediately for the switching of the clock source, but only in the delay time of the continuous detection of the current tracking source failure, only that the current tracking source is indeed lost, the clock source to switch. And there is a delay time timer for each clock source.

Waiting for the recovery time refers to the synchronization clock signal in the failure state becomes effective, in the source selection module that is necessary to wait before the effective time, generally waiting for the recovery time in the range of 0-12 minutes, the default value is 5 minutes. Only if the clock source is continuously valid during the recovery time is the source considered to be valid and selected and switched by the clock source selection module.

These waiting times are to avoid the phenomenon of clock source error reversal.

6 In the hold mode, what are the types of holds? And the difference between them?

A: There are mainly two kinds of holding modes, which are normal holding mode and permanent holding mode; normal holding mode is also called normal holding mode, in tracking mode, every time interval T (the time interval T is related to the length of the holding data buffer, the principle is that it needs to keep the information for at least 24 hours, and the general T = 9 seconds), the frequency information of the timing reference will be saved in the data buffer successively according to the time, and then when it enters the holding mode, every time interval T will take out the saved data from the buffer from back to front as the timing reference, until it finishes taking the data in the array. After entering the hold mode, the saved data will be taken out from the buffer from back to front at every interval T as the timing reference until the data in the array is taken out to enter the free-running mode. In this holding mode, the actual holding time cannot be infinitely long due to the limitation of the size of the data buffer, but it must be guaranteed to be more than 24 hours.

Permanent hold mode: that is, in the tracking mode, every interval of time to save the frequency information of the timing reference, when entering the hold mode, the last period of time to save the frequency information as the timing reference, this hold mode mode can be infinitely long.

7 In those cases, the clock source generates SYN_BAD alarm?

A: The clock source generates the SYN_BAD alarm in the following two main cases:

1 The DA value generated by the current tracking source through the DSP is not within the normal range of 100 to F00, and thus the current tracking source reports the SYN_BAD alarm.

2 With the frequency deviation detection function activated, an excessive frequency deviation of the clock source is detected in the clock priority table, thus generating the SYN_BAD alarm.

8 Main differences between REG and non-REG devices?

A: REG devices are only CRG clock boards in OSN products now; other cross-clock boards are non-REG devices; the main differences between these two are as follows:

1 appearance and logical slot on the difference: REG equipment, although the use of sub-frame and 2500 network element equipment, when the REG equipment is used in the main control, clock board SSQ1CRG, and 2500 network element equipment is used in the main control, cross, clock, line board SSN1CXL

2 The difference in the use of functions: REG is to support 2.5G and 10G pure REG equipment, STM-16 and STM-64 system regenerator, only to complete the signal regeneration function. It can not configure services and protection; while 2500 non-REG devices have high and low order crossover capability, and can be configured with various protections such as SNCP/TPS/MSP.

3 The difference between the functions of the line boards used: REG borrows NGSDH line veneer, 2.5G veneer borrows SSN1SL16 and SSN1SF16, and 10G veneer borrows SSN1SL64 and SSN1SF64; in REG mode, the line boards are in the regenerative segment loopback mode to realize the east-west penetration of the service. In addition, in REG mode, only the frame header and regeneration segment overhead are processed, and other overhead bytes and pointers are transmitted transparently.

9 What is the difference and connection between LTI and SYNC_C_LOS alarms?

A: LTI alarm indicates the loss of synchronization source alarm, that is, in the configured clock priority table, configured in addition to the internal source of the clock source, when all the external sources do not meet the selected conditions, the current is still working in the hold or free oscillation mode, then the alarm is reported;

The SYNC_C_LOS alarm indicates that there is a clock source in the priority table that is lost and generates an alarm; this alarm is reported only if there is an external source in the configured clock priority table that has a logical state of nonexistence;

The two are related: when all external sources in the clock priority table are configured to report the SYNC_C_LOS alarm, then there must be an LTI alarm reported; conversely, when there is an LTI alarm, there is not necessarily a clock source reporting the SYNC_C_LOS alarm.

10 In the new frequency bias detection scheme, what are the principles followed for its frequency bias detection?

A: In the new frequency deviation detection scheme, in order to prevent the phenomenon of clock source wrongly inverted due to the open judgment or misjudgment of the detection source, the first principle is: after detecting all the clock sources in the frequency deviation detection table, then make the selection of the clock source. The second principle: in the case that there are three or more external sources in the frequency offset detection table, only then can the main and backup be switched; the last principle: try to carry out the source to switch first, and then consider the principle of main and backup to switch.

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