Operator M is using OSN3500 V2R11C00 to group 10GE packet plane networks using PEX1.

When the service processing board is SSN1PEG8 or SSN1PEG16, the FE ports of interface boards SSN1PETF8 and SSN1PEFF8 cannot reach the full-rate bandwidth when the service processing board is SSN1PEG8 or SSN1PEG16.

The test was conducted using Smartbits 600B, first using the interface board with SSN1PEG8 and then using the interface board with SSN1PEG16, and the test results are shown in Appendix 1.

From the test results, it can be seen that, in general, the longer the packet length, the closer to the line speed; however, the pass rate and packet length is not a strictly linear relationship between certain packet lengths (such as integer multiples of 8, and business processing chip speed limit algorithms related to) can be passed!

The worst case is 94.63% with SSN1PEG8 processing board and 96.03% with SSN1PEG16 processing board. While the actual network bearer packet length is variable, the test results of random packet length are 99.42% and 98.04% respectively.

None

For the random packet length, the result of our test has less influence on the actual application of the customer, because the test instrument uses full bandwidth service test, and the actual service of the customer can seldom reach 100M full bandwidth, so the single board can meet the actual application of the customer.

Customers are concerned about bandwidth exceeding, resulting in transmission packet loss and no alarm reporting problems, which can be solved in the V2R11C00SPC300 version. In this version, the FE port of the interface board supports FLOW_OVER alarm, and the alarm reporting threshold is 80Mbps (excluding the 20-byte leading code and frame gap). Calculate, if the service message is 128 bytes, then if the port service traffic is greater than 92.5Mbps, the FLOW_OVER alarm will be reported to alert the customer. During service planning, if an alarm is reported to remind the customer that the bandwidth may not be sufficient to support the current service, the customer needs to re-plan the bandwidth, such as sharing to multiple FE ports or carrying the service through GE ports.

The eight FE ports on the
interface board are divided into one GE port on the service processing chip using channelization technology. When one of the FE ports exceeds the speed limit and is back-pressurized, the chip can only back-pressurize the entire GE port, resulting in the other FE ports being back-pressurized at the same time. Therefore, in the implementation, the FE is set to not support backpressure.

The so-called channelization is not really physically splitting the GE port into multiple FE ports, but through multiplexing technology to multiplex multiple low-rate channels in the timing, and then through the rate conversion to complete the conversion, so in order to identify the data of the low-rate channel in the high-rate channel, some special marking is needed to complete the business processor chip adopts a layer of all incoming telegrams to add a layer of channelization vlan The service processing chip adopts the method of adding a layer of channelized vlan to all incoming messages.

This leads to an increase in packet length. When sending packets at full rate, the packet rate of the outgoing port exceeds the maximum rate that the PHY chip can support. This is not a problem for GE ports that support backpressure; when the rate exceeds the PHY chip's limit, the service processing chip that receives the backpressure signal reduces the packet rate to meet the PHY chip's sending capacity; for FE ports that do not support backpressure, packets that exceed the PHY chip's sending capacity are randomly discarded by the PHY chip.

The PHY chip discards messages without distinguishing the priority of the message, and the problem of packet loss occurs for high-priority messages. For example, protocol messages are discarded, resulting in protocol jitter and causing serious problems. In order to avoid this situation, in the implementation, the speed limit processing is done in the downstream of the service processing chip, and low-priority messages are preferentially discarded when the traffic is too large, so as to ensure that high-priority messages pass as far as possible, so as to avoid randomly dropping packets at the back of the PHY chip.

R&D is expected to release a new version in Q2 2012 to solve this problem. Before the problem is solved, it is necessary to inform customers in advance to do business planning. If the business traffic is close to 100M, it is better to share the business to two or more ports.