Optix OSN3500 SXCSA Clock Crossover Board Supports functions and features such as service scheduling, clock input and output. The basic function is to accomplish 200Gbit/s VC-4 high-order crossover, 20Gbit/s VC-3/VC-12 low-order crossover, and 155Gbit/s access capability. Provide flexible scheduling capability of services, support non-blocking full cross, support multicast and broadcast services. Provide communication function with other single boards. Supports 1+1 hot backup of single-board crossover and clock unit, and the protection mode is non-recovery by default.

Problem Description

Use the SSN1GXCSA and SSN1SXCSA02 single boards respectively to perform the following clock hold mode tests:

1. Configure two external clock sources to track the first clock for a long time (greater than 24 hours);

2. Disconnect the first external clock and switch the network element clock tracking to the second external clock;

3. Disconnect the second external clock after 30 seconds of tracking.

The SSN1GXCSA single board can enter the hold mode after the second external clock is disconnected;

SSN1SXCSA02 single board directly enters the free oscillation mode after disconnecting the second external clock and does not enter the hold mode.

A customer is quite incomprehensible, and determined that the SSN1SXCSAO2 single board is defective and needs to be rectified.

Processing

Discrepancy analysis:

Analyzing the code reveals differences in the two single board clock implementation schemes:

1, SSN1GXCSA single board using the old clock realization scheme, the original clock save data will not be cleared when the clock source is switched;

2, SSN2SXCSA02 single board using the new clock implementation scheme, the clock source switching will re-save the clock data information of the new tracking source, while clearing the original clock save data.

3, in the above two modes, the single-board save hold data are acquired every 9 seconds, a total of about 24 hours need to be acquired to ensure that the 24-hour hold time. For the second program, if the clock source is switched after 30 seconds to enter the hold mode, at this time only about 3 hold data, so only a short period of time into the hold mode will enter the free oscillation mode.

4, in the ITU-T recommendations do not have a clear definition of the meaning of the hold mode, but only stipulates the hold mode SDH equipment needs to meet the clock performance indicators. From the point of view of the recommendations, both old and new clocking schemes are in line with the recommendations;

5. but the SDH principle and synchronization specification defines the hold mode as follows:

"When all timing references are lost, the slave clock can enter the so-called hold mode. At this time, the slave clock uses the last frequency information stored before the loss of timing reference signals as its timing reference and works to ensure that the slave clock frequency has only a small frequency deviation from the reference frequency over a long period of time, so that the sliding damage remains within the permissible index requirements"

Therefore, the design of the new clock scheme is more reasonable from the definition in the SDH synchronization specification. The old program in the clock source switching clock data is still preserved after the original tracking source information, then into the hold mode and does not truly reflect the last clock tracking source (i.e., all the clock sources before the loss of the clock performance), which in fact, indirectly lost the significance of the system clock hold mode.

However, in practice, in general, no matter which clock source is tracked, its frequency deviation is within a very small range, even with the old scheme, it will not produce enough to affect the business of the frequency deviation or phase jumps, and the current network test of this scenario (two tracking sources lost one after another to cause the clock to enter the hold mode) is very rare, so the old scheme is basically the same in the external embodiment and the new scheme.

6, OSN3500 device R8C02B01L version of the use of old and new clock program as follows:

Old program boards: SSN1GXCSA, SSN1EXCSA, SSN1UXCSA/B, SSN1SXCSA/B-01, SSN1IXCSA/B;

New Program Veneer: SSN1SXCSA/B-02

Root Cause Analysis

During the SSN1SXCSA02 single-board test process, the single-board clock save data information is queried and found that when the clock source is switched (disconnecting the first external clock and inverting to track the second external clock), the single-board clock save data information is cleared to zero:

For SSN1SXCSA02 single-board, the clock source is reversed to the second channel after the original saved clock data information are cleared, and track the second external time is not long enough (only 30 seconds), so after disconnecting the second external clock single-board does not save enough clock information, and thus directly into the free oscillation state, did not enter the hold mode;

SSN1GXCSA single board is different, after the clock source switching its clock holding data has not been cleared to zero, its clock information is still the clock information of the first road, so in the brief tracking of the second road and then disconnect can still enter the hold mode;

Recommendations and Summary

The problem of the different test results of the clock hold mode of the two cross boards is due to the different clock realization schemes of the two single boards (the SSN1GXCSA single board adopts the old clock scheme; the SSN1SXCSA02 single board adopts the new clock scheme);

And from the practical application of the new clock program is more reasonable, more reflective of the true meaning of the clock hold mode.

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