Description of the problem

An engineer expands two SSN1EMS4 single boards in slots 6-13 of a Huawei OSN3500 device. After the expansion is completed, the spare cross board, slot 10 SSN1GXCSA, frequently reports HSC_UNAVAIL alarms. Query the host software version: 5.21.18.50P01, single board version: 7.15. engineers have replaced two EMS4 single boards, replaced the main cross board, replaced the subrack, but did not solve the problem.

Alarm message

0:58:30 0x02 0x01 0x0a 0xff 0xff

230632 10 HSC_UNAVAIL MJ end 2011-06-07 10:58:42 2011-06-07 11:16:39 0x02 0x01 0x0a 0xff 0xff

230640 10 HSC_UNAVAIL MJ end 2011-06-07 11:17:59 2011-06-07 11:23:17 0x02 0x01 0x0a 0xff 0xff

230642 10 HSC_UNAVAIL MJ end 2011-06-07 11:23:54 2011-06-07 11:30:26 0x02 0x01 0x0a 0xff 0xff

230648 10 HSC_UNAVAIL MJ end 2011-06-07 11:31:02 2011-06-07 11:59:18 0x02 0x01 0x0a 0xff 0xff

Processing

According to the above analysis, the possible reason for the HSC_UNAVAIL alarm reported on the backup crossover of this network element is that the quality of the first external clock tracked by this network element is very poor, resulting in the jitter of the clock and the frame header output from the crossover board to the ssn1ems4 board, which results in the bad crossover reported by the ssn1ems4 board. The problem is solved after setting this network element to track the internal clock source. Contact the customer to provide a stable external input clock source.

Root cause

From the alarm parameters, it seems that the service board has detected a bad spare master control board. Query 10-ssn1gxcsa black box BB9 and confirm that the two newly expanded EMS4 boards are the ones reported as bad cross boards.

54975 2011-6-7 11:46:19 0x56 Level:3, XcsXcpModule.cpp, Line:2589, Report Xcs Bad BDNum=2, BDId: 6 13

54976 2011-6-7 11:46:19 0x56 Level:3, XcsXcpModule.cpp, Line:2610, Report OthXcs Bad BDNum=0

54977 2011-6-7 11:56:36 0x56 Level:3, XcsXcpModule.cpp, Line:2589, Report Xcs Bad BDNum=2, BDId: 6 13

54978 2011-6-7 11:56:36 0x56 Level:3, XcsXcpModule.cpp, Line:2610, Report OthXcs Bad BDNum=0

Since the currently used version 7.15 has solved the problem of false detection of bad crossover (SC0000610778), software factors are excluded.

By using the serial port to capture the printout information from the EMS4 single board, it was found that the ClkLineState register of ssn1ems4 is jittering (ClkLineState = 0x0 means normal, ClkLineState = 0x1 means abnormal).

********************************************************************************

Current working board: 0x0

Motherboard:OnlineStateA = 0x0, OKStateA = 0x0, ClkLineState = 0x0, BusState = 0x0

Spare Board:OnlineStateB = 0x0, OKStateB = 0x0, ClkLineState = 0x1, BusState = 0x0

StatusXcsA = 0x0, StatusXcsB = 0x1

********************************************************************************

********************************************************************************

Current working board: 0x0

Motherboard:OnlineStateA = 0x0, OKStateA = 0x0, ClkLineState = 0x0, BusState = 0x0

Spare Board:OnlineStateB = 0x0, OKStateB = 0x0, ClkLineState = 0x1, BusState = 0x0

StatusXcsA = 0x0, StatusXcsB = 0x1

*****************************************************************************

ClkLineState = 0x1 indicates that ssn1ems4 detected a bad 38M clock or 2K frame header sent from cross 10.

Confirm that the signal sent by the crossover board to the EMS4 veneer does have jitter.

Further analysis of the data reveals that the DA value of the network element cross single-board clock is unstable and fluctuates greatly, so it is suspected that the cross 38M clock and 2K frame header jitter reported by the ssn1ems4 single-board is due to the poor quality of the tracked clock clock:

9-829:szhw [MSW-02 ][][2011-07-27 11:15:59+02:00]>

:cfg-get-synstateda:9,0

SYN-STATE-DA

PLLTYPE STATE DA

0 1 2628

Total records :1

#9-829:szhw [MSW-02 ][][2011-07-27 11:15:59+02:00]>

:cfg-get-synstateda:9,0

SYN-STATE-DA

PLLTYPE STATE DA

0 1 2065

Total records :1

#9-829:szhw [MSW-02 ][][2011-07-27 11:16:00+02:00]>

:cfg-get-synstateda:9,0

SYN-STATE-DA

PLLTYPE STATE DA

0 1 1969

Total records :1

#9-829:szhw [MSW-02][][2011-07-27 11:16:00+02:00]>

:cfg-get-synstateda:9,0

SYN-STATE-DA

PLLTYPE STATE DA

0 1 2053

The clock tracked by this network element is the first clock, and the quality of this first external clock is poor, as shown by the constantly fluctuating DA value:

#0x9033d:cfg-get-cursyn:9;.

CUR-SYN : 0xf001

Recommendations and Summary

The chip on the EMS4 single board of Huawei OSN3500 devices has high requirements for clock signals, and the EMS4 single board detects the frame header and 38M clock signals every 50ms, and reports them once they are detected to be bad, and starts to report them to be good only when contacting 5 queries that are all good.

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