• In SDH transmission networks, SSM is transmitted through the lower four bits b5 to b8 of the S1 byte in the SDH segment overhead; whereas in BITS devices, SSM is transmitted through a bit in the first time slot (TS0) of the 2 Mbit/s clock signal. It can be seen that the 2MHz clock signal cannot carry SSM information.

  It should be noted that there is a difference between the concepts of SSMB and S1 byte: SSMB is a set of message codes used to indicate the clock quality level, as shown in Table 1; whereas the S1 byte is a byte in the SDH segment overhead, and the lower four bits of the S1 byte are the SSMB.

  Table 1 Synchronization status message encoding

  Z1 (b5-b8]	S1 byte	SDH synchronization quality level description
  0000	0x00	Synchronization quality agnostic (UNKNOWN)
  0001	0x01	Reserved
  0010	0x02	G.811 Clock Signal (PRC, generally cesium clock)
  0011	0x03	Reserved
  0100	0x04	G.812 Transfer office clock signal (SSUA, typically rubidium)
  0101	0101 0x05	Reserved
  0110	0x06	Reserved
  0111	0x07	Reserved
  0x07 Reserved	0x08	G.812 Local Office Clock Signal (SSUB, typically rubidium or crystal clock)
  1001	1001 0x09	Reserved
  1010	0x0a	Reserved
  1011	0x0b	Synchronization device timing source (SEC) signal (typically a crystal clock)
  1100	0x0c	Reserved
  1101	0x0d	Reserved
  1110	0x0e	Reserved
  1111	0x0f	Should not be used for synchronization (DNU)

  When the clock board is powered up, the default clock level of all reference sources is UNKNOWN. the order of SSM level is: PRC＞SSUA＞LNCSSUB＞SEC＞UNKNOWN＞DNU. if the SSM level of a reference source is DNU and SSM is involved in the control, the reference source of the road is not selected for protection inversion.

  The SSM level of the output signal depends on the clock source being tracked. When the operating mode of the clock is tracking, the output SSM level is the same as the SSM level of the tracked clock source, and when the operating mode of the clock is not tracking, the output SSM level is SEC.

  For the line clock source, the SSM can be extracted from the line board and reported to the main control board, which then sets the SSM of the line clock source to the clock board; or the SSM of the road reference source can be forced to be configured by the main control board.

  For the BITS clock source of the clock module, if it is a 2.048Mbit/s signal, the clock module can extract the SSM from the signal, and if it is a 2.048MHz signal, the SSM level is set manually by the user.

Relevant single boards involved in physical layer clock protection inversion

To realize the clock protection inversion, the protocol needs to be started and completed with the participation of each single board. In clock protection inversion, each single board accomplishes the following functions.

• Line board

  Responsible for SSM insertion and extraction. The optimal source SSM value of the device sent from the clock board is set up on the line board side to be distributed outward in each synchronized physical port; the line board is responsible for processing the SSM value received from each synchronized physical port.

• Clock Board

  The clock board performs functions such as extracting the SSM of the external clock and performing the inversion of the tracking clock source. After the clock board receives the SSM from the line board, it decides which clock source to track according to the protocol, and then performs clock protection inversion and sends the SSM of the current clock source to other line boards at the same time.