告警信息

无

Process

The company urgently set up a research team, and then analyzed the cause.
The R & D research confirmed:
Difference analysis:
Analysis of the code found that there are differences between the two single-board clock implementation scheme:
1, SSN1GXCSA single-board using the old clock implementation scheme, in the clock source switching the original clock to save the data will not be cleared to zero;
2, SSN2SXCSA02 single-board using the new clock implementation scheme, the clock source will be re-saved after the switch to save the new tracking source clock data information, while clearing the original clock to save data information, while clearing the original clock save data.
3, in the above two modes, the single-board save hold data are collected every 9 seconds, a total of about 24 hours to ensure that the 24-hour hold time. For the second program, if the clock source is switched after 30 seconds into the hold mode, this time only collected about 3 hold data, so only a short period of time into the hold mode will enter the free oscillation mode.
4, in the ITU-T recommendations do not have a clear definition of the meaning of the hold mode, but only stipulates the hold mode SDH equipment needs to meet the clock performance indicators. From the point of view of the recommendation both old and new clocking schemes meet the requirements of the recommendation;
5. However, the SDH Principle and Synchronization Specification defines the hold mode as follows:
"When all timing references are lost, the slave clock can enter the so-called hold mode. At this time, the slave clock uses the last frequency information stored before the loss of timing reference signals as its timing reference and works to ensure that the slave clock frequency has only a small frequency deviation from the reference frequency over a long period of time, so that the sliding damage is still within the allowable index requirements"
Therefore, the new clock scheme is more reasonable in terms of the design from the definitions in the SDH synchronization specification. The old scheme in the clock source switching clock data is still preserved after the original tracking source information, then into the hold mode does not truly reflect the last clock tracking source (i.e., all the clock sources before the loss of the clock performance), which in fact indirectly loses the significance of the system clock hold mode.
However, in practice, in general, no matter which clock source is tracked, its frequency deviation is within a very small range, even with the old program, will not produce enough to affect the business of the frequency deviation or phase jumps, and the current network test of this scenario (two tracking sources are lost one after another to cause the clock to enter the hold mode) is very rare, so the old program is basically the same in the external embodiment of the new program up.
6, OSN3500 device R8C02B01L version of the use of the old and new clock program board as follows:
Old program board: SSN1GXCSA, SSN1EXCSA, SSN1UXCSA/B, SSN1SXCSA/B-01, SSN1IXCSA/B;
New program board: SSN1SXCSA/B-02

Root Cause

Root Cause Analysis
In the SSN1SXCSA02 During single-board testing, the single-board clock save data information was queried, and it was found that the single-board clock save data information was cleared when the clock source was switched (disconnecting the first external clock and inverting it to track the second external clock):
For
For SSN1SXCSA02 board, the original clock data information is cleared after the clock source is reversed to the second channel, and the tracking time of the second external clock is not long enough (only 30 seconds), so the board does not have enough clock information saved after disconnecting the second external clock, and thus directly enters the free oscillation state. 从而直接进入了自由振荡状态，没有进入保持模式；
SSN1GXCSA单板则不同，时钟源切换后其时钟保持数据没有被清零，其时钟信息仍然是第一路的时钟信息，因此在短暂跟踪第二路后再断开依然可以进入保持模式；

Solution

Recommendations and Summary

The problem of different test results of clock hold mode for the two crossover boards is due to the difference in the clock implementation scheme of the two single boards (SSN1GXCSA single board adopts the old clock scheme; SSN1SXCSA02 single board using the new clock program);
and from the actual application of the new clock program is more reasonable, more reflective of the true meaning of the clock hold mode.